FPGA Beginner’s Series, 12: Driving a 7-Segement Display

It just occurred to me that learning to program FPGAs is making me feel young again. It’s not taking years off my countenance or anything, but I’m once again working with circuits I was building in my high school
electronics class back in the age of dinosaurs and dweebs.

In this column, I’ve added a binary to seven-segment decoder to the binary counting configuration I used in my previous blog. The seven-segment display I’m using is an old FND500 that I purchased in 1980 when building my first computer — a CDP1802-based singleboard
thing. My primary objectives with this project are to build on my starting project by adding more functions and to get something running that I can use to learn about the ChipScope virtual logic analyzer (a device discussed here before).

I’ve used almost all the available I/O on my Spartan FPGA, but I was able to bring out both the binary count and the seven-segment hex count. My push-on/push-off switch starts and stops the count, while my plain momentary contact push-button switch activates the decimal point. I’ve uploaded the complete UCF and Verilog file here, so you can follow our “create project” steps from previous blogs to start with working code before heading to ChipScope. I named my project “FND500count.” You can skip the “New Source Wizard” steps and just put the Verilog file and UCF into your empty project as complete source files. Copy the two files, “7-segment count.v” and “7-segment.ucf,” into a “source” folder in your project folder.

7-segment folders

After that, you just add the Verilog file, followed by the UCF file, into the project through the “Add file” option.

7-segment add file

Since we’ll be using ChipScope once this is all done, actual hardware isn’t really necessary. However, if you want to build it up, take a look at the picture at the start of this article.

In our previous sample code, the binary counting came out on the four LEDs built into the
Spartan 6 LX9 board. I started out using that sample code (both the Verilog file and the UCF).
For this exercise, I changed the binary count to drive four external LEDs, just to make it easier
to see both the binary count and the seven-segment count.

I had to change a few things in the UCF. For example, the “LOC” chip pin values for COUNTING_LEDS have changed to represent the pins connected to the header on the PCB. (Refer to Header J5 on Sheet 5 of
the Spartan schematic.)

As illustrated in the image below, I also changed the IOSTANDARD constraint from “LVCMOS18” to “LVCMOS33.” The four on-board LEDs are connected to Bank 3 of the Spartan chip, and this bank has 1.8-volt pins (Sheet 7 of the schematic). However, the headers J5 and J4 run from pins in Bank 1, which has 3.3-volt pins, hence “LVCMOS33.” I left “DRIVE” at 8mA. With an 8mA forward current and 1.7-volt forward voltage on my LEDs, I would need a 220-ohm resister to match everything up. The Spartan 6 chip will drive currents of 2, 4, 6, 8, 12, 16, and 24 mA. My LEDs will take a maximum of 20mA, but they light reliably with quite a bit less, so 8mA is fine for my parts.

7-segment change in IOSTANDARD

I put my momentary contact switch between pins 4 and 6 (chip pin E18 and Vcc) of header J4. The push-on/push-off switch goes between pins 10 and 12 (chip pin F18 and Vcc), also on header J4.

7-segment switch locations

The real spaghetti connects to my solderless breadboard. I’m using that ancient FND500 seven-segment LED I told you about earlier. This is a common cathode LED, so you’ll want to use the same if you plug in a different device. The pin-outs for this part are shown below. Your pin-outs may differ if you have a different part.

FND500 pin outNow that you have the project created and the hardware built (or visualized in your head), you can synthesize, implement, generate, and configure as we’ve done in past blogs. The result should look something like mine, which I’ve captured in the following video:

The new construct in the Verilog file (lines 80 to 99 in my file) is the binary to seven-segment decoder. I feed it (SEG_OUT) the same four bits (led_count[28:25]) that I feed the binary leds (COUNTING_LEDS). It introduced the reserved words “assign” and “case.” It also brought in the use of the term “reg” instead of “wire” back up on line 27. I still need to do a bit more reading before I can explain how this all works, but that will come later — unless anyone wants to read up and explain it to the rest of us by posting comments to this blog.

In my next post, I’ll bring up ChipScope, and I’ll explain the reg, assign, and case keywords in more detail.

FPGA Beginner’s Series, 11: Adding in the Switches

As you may recall, we have progressed beyond the light-emitting diode (LED) flashing tutorial that was provided with the Avnet Spartan-6 LX9 MicroBoard. Now we wish to plug some external switches into our FPGA development board and then use these switches to “Start” and “Stop” the
count sequence being displayed on the LEDs.

In my previous column, we got the UCF (user constraints file) taken care of, and we also got a sneak preview of the hardware (LEDs and switches) we are going to connect to our development Programmable Planet whats next - generated V codeboard. (See: Discovering FPGAs: Playing With LEDs & Switches.)

The next step is to decide what needs to be done with the *.v (Verilog) file that was automatically generated by the system. Let’s use the ISE Design Suite to look at this generated code as illustrated here:

ISE gave us a start, but there are quite a few things missing. First, we have inputs and outputs defined, but they aren’t really connected up to anything. To do that, add the reserved word “wire” to the inputs and outputs, as shown in the following image:

Programmable Planet whats next - generated V code

Next, copy and paste all of the code from the “ledflash_ISE_ver.v” example file that we completed in an earlier column, Discovering FPGAs: Loading the .BIT File. Copy the code from line 10 through to the end of the file and paste it in starting at line 31 of the new code. If you end up with two “endmodule” statement lines, just delete one of them.

Programmable Planet whats next – copy old code

Don’t run ahead and synthesize, implement, generate, and configure yet, because you won’t get very far and you will likely be a little disappointed. Before doing that, we first have to tell the Verilog code to do something with the LEDs and switches.

For the first shot, we’re just going to connect the switches directly to the LEDs. That’s pretty easy to do in actual hardware, and it’s also reasonably easy to achieve in an FPGA. Down toward the bottom of the code, change the name “LED” on line 76 to match the “COUNTING_LEDS” that we renamed it to. Also, change the bit ranges to match the fact that we’re only counting with four LEDs again. Also, add an “assign” line for each switch/LED pair. When you are done, lines 76, 77, and 78 will read as follows

Programmable Planet whats next - assign switch inputs

You probably noticed that I inverted the setting for switch input “STOP_COUNT” with the “NOT” sign “!” (this character is commonly referred to as a “bang,” “ping,” or “shriek”). In reality, this wasn’t really necessary, but it’s there now and it may be important in later exercises.

Now we can synthesize, implement, generate, configure, and program as we did earlier in series. In summary, what we’ve done is:

  • Connect pins 4 and 10 of header block J4 to the FPGA as inputs
  • Connect pins 4 and 10 of header block J5 as outputs
  • Use the FPGA to connect the two sets so that a switch setting applied to one header pin
    routes into the FPGA and back out to a different header pin

Finally, we’ll do one more thing. Go back to the Verilog file and — at line 73 — insert the statement “if (START_COUNT)” as shown below:

Programmable Planet whats next - if statement

Try it and see if you correctly predicted the behavior.

One of the risks of having a beginner (such as myself) teaching other beginners is that there’s always the possibility that I’ll miss an important detail, make incorrect statements, or just not always understand why I’m doing something. This Website being a community effort, I encourage anyone who catches me doing any of the above to correct me and to add to what I’ve written.

Along these lines, I submit the reserved word “wire” that we added in earlier. All of the documentation I’ve read thus far hasn’t been all that clear, and the examples I’ve looked at aren’t consistent in the use of this word. My understanding is that the word “wire” is telling the system to route a wire between the physical pin, as defined in the UCF, and the symbol in the Verilog code, e.g., “USER_RESET,” “START_COUNT,” etc

 

FPGA Beginner’s Series, 10: LEDs and Switches

In my last few blogs, I’ve taken an existing command-line tutorial and brought it up in the Xilinx ISE development environment. That’s an important first step, but now it’s time to start doing something of my own. I’ll begin simply, borrowing heavily from the example we just completed. Basically, I’m going to edit the counter back to four light-emitting diodes (LEDs) — the way it was before we modified it — and then add in some logic to “Start” and “Stop” the count
sequence being displayed on the LEDs.

Today, we are going to:

  1. Create a new project called “led_input”
  2. Use most of the code from our prior example
  3. Change a few names to better fit what we’re doing
  4. Take the two extra LEDs out of the register and turn them into independent outputs
  5. Add two switch inputs
  6. See what happens next…

You will need:

  1. Your Spartan-6 LX9 development board plugged into your computer
  2. The two LEDs with pigtail wires that we created in our earlier columns
  3. Two switches with pigtail wires soldered to them so they can be plugged into the header
    block on the FPGA board
  4. The old code from “ledflash_ISE_ver” (or the “led_input.v” file from this blog) opened in
    a text editor

To start, we need to follow the steps I outlined in an earlier column. (See: Discovering FPGAs: Bringing Up the IDE.) Start up ISE and create your empty project (Steps 1 through 4 in that prior column). The only difference so far is that this one will be named “led_input.” Next, when you open the New Source Wizard, we’ll start to see some differences. Define your ports as shown in the above image.

“CLK_66MHZ” and “USER_RESET” are the same as in our last project. The inputs “START_COUNT” and “STOP_COUNT” will be our new switch inputs. I changed the name of the port from plain “LED” to “COUNTING_LEDS” because non-descriptive names kind of drive me nuts. This is especially true in the case of something like “LED” when I also have to reference the physical light emitting diodes. “COUNTING_LEDS” is still marked as a bus, but the MSB is now 3 instead of 5.

“LED_STARTED” and “LED_STOPPED” will be the extra LEDs (you see — now I can just say “LEDs,” instead of spelling out the acronym, and not get confused) that we stuck into the header J5 in an earlier column. This time, however, they aren’t assigned to be part of the main port; instead, they will be used as visual indicators displaying the status of the two switches we are going to add.

Take a close look at the UCF (user constraints file) in the following image. It has a lot in common with the “ledflash_ISE_ver.ucf” we used in prior blogs. To create it here, go to the project menu and select “New Source.” When the New Source Wizard comes up, choose “Implementation Constraints File” and again, name it, “led_input.” Finally, enter the constraints code shown in the image below:

Programmable Planet whats next - led_input UCF

The switch “START_COUNT” will go into pin 4 of header J4, while switch “STOP_COUNT” will be plugged into pin 10 of J4. Pin 4 on the header is connected to pin E18 on the FPGA chip, while pin 10 on the header is connected pin F18 on the FPGA. Both of these pins are in the 3.3 volt section of the FPGA. There are no hardware pull-down resistors on the board for the header pins, so we’ll indicate that we wish to activate these in the FPGA via the UCF employing the same technique that is used for the “USER_RESET” signal.

We’ll finish this up in my next blog, but before we move on, take a look at the hardware we’ll be using. The red square switch is a push-on / push-off switch, which connects between pins 4 and 6 of header block J4.

Programmable Planet whats next - switches and leds

The black round switch is a momentary contact, connecting between pins 12 and 10 of J4. The
LEDs, as in our earlier columns, connect between pins 4 and 5 and between pins 10 and 11 of
header block J5.

Programmable Planet whats next - header blocks

FPGA Beginner’s Series, 9: Loading the .BIT file

In my last blog, I used the IDE (Integrated Development Environment) supplied with my FPGA development guide to walk through the process of creating the .BIT configuration file. In this installment, I’ll guide you through the process of of loading the .BIT configuration file into the FPGA.

OK, the state-of-play following my previous blog is that I now have the “ledflash.bit” file in the “ledflash_ISE_ver” folder on my computer. The Spartan-6 development board is sitting on my desk. There’s a cable connecting my computer to the development board. I say “Let’s go!” Basically, what we’re going to do is to perform the following tasks:

  1. Open up a new piece of software called Impact
  2. Tell this application how to find the Spartan-6 board
  3. Locate the configuration “ledflash.bit” file
  4. Load the “ledflash.bit” file into the FPGA
  5. Watch the LEDs on the development board count in binary

As I say, we will be using a new piece of software called Impact, but we will still access this through the ISE, which means we need to start up the ISE. If your “ledflash_ISE_ver” project from my previous column isn’t loaded automatically, load it up now. Next, click the little “+” (plus sign) next to the “Configure Target Device” item, as seen in the image below.

Loading configuration into FPGA - open configure

Double-click the “Manage Configuration Project (Impact)” item. Doing so opens another piece of software called — perhaps not too surprisingly — “Impact.” This is the application that will actually be loading the “ledflash.bit” file into the FPGA. Note that you will most likely have to manually tell the software where to find your cable. I had assumed the software would find this automatically, or at least would only need to be told once, but it seems to need me to tell it every time.

Loading configuration into FPGA - Launch iMPACT wizard

Launch the wizard, as shown in the image above. The first window will have a dropdown menu under the text “Configure devices using Boundary-Scan (JTAG).” Set the drop-down to “Enter a Boundary-Scan chain manually” and click “OK.”

Loading configuration into FPGA - chain manually

We’re almost done, I promise. Observe a window titled “Boundary Scan” with blue text saying: “Right-click to Add Device or Initialize JTAG chain.” Follow the blue instruction text and rightclick in the big open “Boundary Scan” window. This will access a small pop-open menu, from which you need to select the “Cable Setup…” item.

Loading configuration into FPGA - iMpact selecting diligent

As shown in the above image, check the box “Open Cable Plug-in…,” leave the drop-down box as “digilent_plugin,” and click the “OK” button. Don’t be surprised if nothing happens after this step because there doesn’t appear to be any feedback at this point.

Again, right-click on the blue text that says: “Right click to Add Device or Initialize JTAG chain.” This time, select “Add Xilinx Device…” from the pop-up menu. You’ll have to hunt down the “ledflash.bit” configuration file that we created as part of my last blog. Hopefully, you will find this in the tutorial directory we created a while back: “My Documents\Xilinx\ledflash_ISE_ver\ledflash.bit.” Once you’ve tracked down the “ledflash.bit” file, click the “Open” button to access its contents.

Loading configuration into FPGA - select ledflash.bit

Finally, right-click on the chip icon and select “Program” from the ensuing pop-up menu. Do not click the blue text. If you do, you’ll get a different menu that doesn’t do what we need.

Loading configuration into FPGA - program

After selecting the “Program” option, you will be presented with one more dialog box titled: “Device Programming Properties — Device 1 Programming Properties.” Just click “OK” and you’re done.

The Impact software will display a rather unsightly blue box with the words “Program Succeeded” in it. At the same time, the LEDs on your Spatran-6 board will start to display a binary count sequence. Congratulations! We are now exactly where we were several weeks ago when we were using the command-line interface.

The difference is that we now know how to use the IDE. This means that when we start creating our own code from scratch, we’ll be more confident that any problems are in our code rather than in the process. And I call that a very good thing.

FPGA Beginner’s Series, 8: Creating the .BIT File

In my previous blog, we completed the most basic framework of our configuration; now, we’re picking up where we left off. My objective in this column is simply to use the IDE to do the same thing we did with our command-line batch files in prior blogs. Before introducing too many variables, I need to be confident that I can use the IDE from start to finish, ending up with my FPGA configured and working.

Learning Verilog (or VHDL) will have to come after this. Based on this objective, I’m not going to go through all of the Verilog code. I’m just going to delete everything in the “ledflash_ISE_ver.v” file and copy and paste the code from our old “ledflash.v” file into here.

So, click anywhere in the Verilog code window, and then type Ctrl-A to select all of the text and — yes — delete it! Delete it all! Next, use your favorite text editor to open the “ledflash.v” file we played with in earlier blogs, select all of the text, copy this text, and then paste it into the “ledflash_ISE_ver” window in the ISE. You should now have “endmodule” as line number 56 in the file, as shown below.

Creating the .BIT file -- Replacing the Verilog.
Creating the .BIT file — Replacing the Verilog.

We’re well on our way to getting back to exactly where we started, so feel free to take a break and have a soda, coffee, beer, or maybe just a glass of water. But first, use your text editor to open up the other file from our earlier discussions — the “ledflash.ucf” file. Chapter 5 of the tutorial discusses what we’ll be doing next. Again, we’re not going to go through all of the tutorial steps here; just the ones needed to get our simple “ledflash” code into the FPGA.

In my last blog, we created a new “.v” source file — this is the one we just filled with our old
code. Today, we’re going to create the new .UCF (user constraints file). Open the Project
menu in the ISE and select “New Source,” which opens up the “New Source Wizard” as shown
below.

Creating the .bit - New Source wizard

In the wizard, select “Implementation Constraints File,” name it “ledflash_ISE_ver.ucf,” and click
“Next” to finish the process. Again, we’re just trying to get a successful compile / configure
here, so I suggest that you do as I am doing, which is to simply copy and paste the contents of
our old “ledflash.ucf” file into this new “ledflash_ISE_ver.ucf” file as shown below.

Creating the .bit - with complete ucf

We’re really getting close now… so skip ahead to the “Mapping the Design” topic on Page 108 in the Xilinx tutorial. I know that we’re bypassing some details that may be important later, but they really don’t contribute to the cause today.

Click on the label “ledflash (ledflash_ISE_ver.v)” up in the ISE Hierarchy box (in the upper left). Then move down in the Process box (center left) and expand the “Implement Design” label as shown below.

Creating the .bit - implement

Cross your fingers, hop up and down on one foot for luck, double-click “Implement Design,” and — over the course of the next couple of minutes — observe the green checkmark icons appear next to the “Implement Design,” “Translate,” “Map,” and “Place & Route” items.

Look back in the process window at the “Generate Programming File” item (the third from the bottom in the image above). If you look at the IDE on your screen, you will see that this does not yet have its own green checkmark. Double-click on the “Generate Programming File” item and observe this check mark appear as shown below.

Creating the .bit - all green

This means that our .BIT configuration file is now complete and is ready to be loaded into the Spartan-6 on our development board. Phew! I don’t know about you, but there seem to be a lot more steps here in the IDE than we had with the command-line operation. However, I suppose that when the configuration spans multiple modules and such, the IDE is the only way to go. Having all of these steps under our belts means that this is a good breaking point. In summary:

  1. We’ve created the project framework in the IDE (my previous blog)
  2. We’ve copied our old Verilog code (“ledflash.v”) into the framework
  3. We’ve copied our old user constraint file (“ledfash.ucf”) UCF into the framework
  4. We’ve skipped a bunch of tutorial steps that are not relevant to this specific exercise
  5. We’ve processed our design (translate, map, place-and-route) to the point where we have a .BIT configuration file ready to be loaded into the FPGA

I wish I could tell you that there was just one more step. However, here in the IDE world, there are still several more steps to go, including the use of another piece of software. So I’m afraid that you will have to wait for my next column for me to wrap everything up — at least as far as this tutorial goes. After that, I’m going to start adding some functionality to the design.

FPGA Beginner’s Series, 7: Bringing Up the IDE

Thus far, I've been working in command-line mode. In this episode, I bring up the IDE (Integrated Development Environment) for the very first time.

When I originally powered up my Spartan-6 LX9 development board, I tried to jump in with the Xilinx IDE (integrated development environment), which they call the ISE (integrated software environment) Design Suite. This seemed to be the logical choice, but I quickly determined that there were just too many variables, and that I needed a little grounding in the actual code before attempting to decipher the inner workings of yet another IDE. Now I'm back to seek my fortune, far away from the trusty command-line.

My board came equipped with ISE version 12.4, so we're going down that path. If you want to work alongside me, click here to download the documentation needed for the next step from the Xilinx Website. We'll be working with the "ISE In-Depth Tutorial," which is second from the top on the page. I'm not using the tutorial's design files but rather will be replicating the command-line work we've done over the last few weeks.

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FPGA Beginner’s Series, 6: Adding LEDs & Modifying the Verilog

From June 25, 2012

Following my success in getting the four light-emitting diodes (LEDs) on my FPGA development board to flash using the provided tutorial, I, examined the contents of the UCF (user constraint file) in a little more detail. In this installment, I'll Duane add two additional LEDs to his development board and modify my Verilog code to drive all six LEDs.

Now it really is excitement time, because we get to modify some Verilog code! Last week we managed to load it into the FPGA, and we saw it perform a binary count on the four red LEDs on the PC board. The next step is to add some extra LEDs along with the code to drive them.

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FPGA Beginner’s Series, 5: More About the UCF

From June 19, 2012:

In my previous article, I discussed how i managed to get all four of the light-emitting diodes (LEDs) on my development board flashing. In this installment, as a lead-up to adding some external LEDs, I'll examine the contents of the UCF (user constraint file) in more detail.

Now I've run the sample code to flash the four LEDs on my development board, and it works. As part of this, I managed to decode the LED pin mapping in the UCF file (that is, the mapping of the signals in the VHDL code to the physical pins on the FPGA that drive the LEDs on the circuit board). Now it's time to get real and actually write some code myself... well, it's almost time...

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FPGA Beginner’s Series, 4: Flashing the LEDs

From June 11, 2012:

Previously, I discovered how the signals in the HDL are related to the physical pins on the FPGA, and how these pins are connected to the light-emitting diodes (LEDs) on the  development board. In this installment, I manage to get all four of his LEDs flashing.

Last week, I more or less found the pins on my FPGA. I'm not talking about the actual pins on the outside of the chip, but rather the mapping to them on the inside. These pins are very tiny, if you must know, and it's very dark inside the chip package. As we left off, everything seemed ready to go so it's time to turn the "ledflash" tutorial files I introduced in my previous column into a configuration bitstream, and then load this bitstream into the FPGA.

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FPGA Beginner’s Series, 3: Sorting Out the Pins

From June 4, 2012:

When I left off, I had just received my FPGA development board (an Avnet Spartan-6 LX9 MicroBoard, which was kindly donated by Xilinx). I opened the package and installed the design software on his computer. In this installment, I discover how the signals in the HDL are related to the physical pins on the FPGA, and how these pins are connected to the light-emitting diodes (LEDs) on his development board.

Given my current level of understanding, the thought of trying to design and implement any form of logical function inside an FPGA is rather daunting, to say the least. Considering the complexity of FPGA design relative to the microcontrollers I’m used to, it makes sense to first find a good starting point and establish a frame of reference.

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