As you may recall, we have progressed beyond the light-emitting diode (LED) flashing tutorial that was provided with the Avnet Spartan-6 LX9 MicroBoard. Now we wish to plug some external switches into our FPGA development board and then use these switches to “Start” and “Stop” the
count sequence being displayed on the LEDs.
In my previous column, we got the UCF (user constraints file) taken care of, and we also got a sneak preview of the hardware (LEDs and switches) we are going to connect to our development board. (See: Discovering FPGAs: Playing With LEDs & Switches.)
The next step is to decide what needs to be done with the *.v (Verilog) file that was automatically generated by the system. Let’s use the ISE Design Suite to look at this generated code as illustrated here:
ISE gave us a start, but there are quite a few things missing. First, we have inputs and outputs defined, but they aren’t really connected up to anything. To do that, add the reserved word “wire” to the inputs and outputs, as shown in the following image:
Next, copy and paste all of the code from the “ledflash_ISE_ver.v” example file that we completed in an earlier column, Discovering FPGAs: Loading the .BIT File. Copy the code from line 10 through to the end of the file and paste it in starting at line 31 of the new code. If you end up with two “endmodule” statement lines, just delete one of them.
Don’t run ahead and synthesize, implement, generate, and configure yet, because you won’t get very far and you will likely be a little disappointed. Before doing that, we first have to tell the Verilog code to do something with the LEDs and switches.
For the first shot, we’re just going to connect the switches directly to the LEDs. That’s pretty easy to do in actual hardware, and it’s also reasonably easy to achieve in an FPGA. Down toward the bottom of the code, change the name “LED” on line 76 to match the “COUNTING_LEDS” that we renamed it to. Also, change the bit ranges to match the fact that we’re only counting with four LEDs again. Also, add an “assign” line for each switch/LED pair. When you are done, lines 76, 77, and 78 will read as follows
You probably noticed that I inverted the setting for switch input “STOP_COUNT” with the “NOT” sign “!” (this character is commonly referred to as a “bang,” “ping,” or “shriek”). In reality, this wasn’t really necessary, but it’s there now and it may be important in later exercises.
Now we can synthesize, implement, generate, configure, and program as we did earlier in series. In summary, what we’ve done is:
- Connect pins 4 and 10 of header block J4 to the FPGA as inputs
- Connect pins 4 and 10 of header block J5 as outputs
- Use the FPGA to connect the two sets so that a switch setting applied to one header pin
routes into the FPGA and back out to a different header pin
Finally, we’ll do one more thing. Go back to the Verilog file and — at line 73 — insert the statement “if (START_COUNT)” as shown below:
Try it and see if you correctly predicted the behavior.
One of the risks of having a beginner (such as myself) teaching other beginners is that there’s always the possibility that I’ll miss an important detail, make incorrect statements, or just not always understand why I’m doing something. This Website being a community effort, I encourage anyone who catches me doing any of the above to correct me and to add to what I’ve written.
Along these lines, I submit the reserved word “wire” that we added in earlier. All of the documentation I’ve read thus far hasn’t been all that clear, and the examples I’ve looked at aren’t consistent in the use of this word. My understanding is that the word “wire” is telling the system to route a wire between the physical pin, as defined in the UCF, and the symbol in the Verilog code, e.g., “USER_RESET,” “START_COUNT,” etc