FPGA Beginner’s Series, 4: Flashing the LEDs

From June 11, 2012:

Previously, I discovered how the signals in the HDL are related to the physical pins on the FPGA, and how these pins are connected to the light-emitting diodes (LEDs) on the  development board. In this installment, I manage to get all four of his LEDs flashing.

Last week, I more or less found the pins on my FPGA. I'm not talking about the actual pins on the outside of the chip, but rather the mapping to them on the inside. These pins are very tiny, if you must know, and it's very dark inside the chip package. As we left off, everything seemed ready to go so it's time to turn the "ledflash" tutorial files I introduced in my previous column into a configuration bitstream, and then load this bitstream into the FPGA.

I've got some important details to explain this week, but before that, I really need to see this board do something. To follow along with me (assuming that you've downloaded and installed the tutorial files), you'll need to jump into the following folder:

...Xilinxledflash_vlog_ise12_4_01implement

(Note that the folder name will be different in a newer version of the ISE.)

The two most important files in this folder are "implement.bat" and "config_S6LX9.bat." Doubleclick "implement.bat" and let it run its course. This compiles the code into the bitstream needed by the chip. After that's done, do the same for "config_S6LX9.bat," which will upload the bitstream into the FPGA.

Success (a drumroll if you please)! If your board is working like mine, you'll see the four red light emitting diodes counting up in binary. It looks kind of like the image shown below. For the purposes of the photograph, however, I've set the four red light emitting diodes to be steadily on so they'll be easier to see (the blue LED indicates the board is powered up).

The development board with all four (red) LEDs lit up
The development board with all four (red) LEDs lit up

Now, back to the subject at hand. Following my previous column, Max posted a comment asking about the confusing naming conventions I had discussed. After summarizing everything nicely, Max asked: "So, is it just me, or is this 0 - 1 - 2 naming convention just a tad confusing?" No Max, it's not just you -- it is confusing. To quickly refresh our minds, in my last blog we looked at a pin-mapping line from the "ledflash.ucf" file as follows:

NET LED<0> LOC = P4 | IOSTANDARD = LVCMOS18 | DRIVE = 8 | SLEW = SLOW ;

It's important to note that this .UCF file follows the Xilinx convention. Other chip makers will likely have their own equivalents. This line is designating a symbol "LED<0>" that is described in your VHDL or Verilog code. It's also defining how that symbol gets outside of the chip. P4 is the pin number on the outside of the FPGA chip. "LOC =" assigns the symbol to the pin, so "NET LED<0> LOC = P4" says that the symbol "LED<0>" maps to the chip pin P4. The rest of the line deals with timing and other details that we can worry about later. The .UCF file also links symbols "LED<1>," "LED<2>" and "LED<3>" to pins L6, F5 and C2. In my head, it helps to visualize "LED" as a bit array with four-bit positions.

The chip used on the board is a Xilinx Spartan-6 XC6SLX9 CSG324AIV1033. It's packaged in a 324 pin 15 x 15mm BGA (ball grid array) form factor. That's a lot of I/O. The chip naming convention identifies pins by row and column: A1, A2, A3... A18, B1, B2, B3... B18 down to V1, V2, V3... V18. The four pins used in the "ledflash" tutorial code are highlighted in the following illustration:

Bottom view of the pins on the chip package
Bottom view of the pins on the chip package

Note that, as in most datasheets, this is a bottom view of the chip package. On the printed circuit board (PCB), the chip will be flipped from left to right. And so we find ourselves on the outside of the chip. Next, we have to find our way across the PCB to the red light-emitting diode with the reference designator D2. Open up page 7 of the schematic diagram "Spartan- 6_LX9_RevB1.pdf" to see how this all connects together. Inside the chip, Xilinx has designated the pin logical name to be "IO_L02p_3." The pin connection (AKA ball on the ball grid array), as we saw earlier, is in row P, column 4. The schematic designer has routed that signal with a PCB net called "FPGA_GPIO_LED1." That net connects to the light emitting diode, D2.

The sample runs - schematic
Page 7 of the schematic

Wow! That's a lot of important details to pull together. Fortunately, once you're past this part, you really only need three pieces of this information as follows:

  1. In your HDL code, "LED<0>" is the part you'll need to know and use.
  2. The pin number "P4" is needed in the .UCF file to map the symbol.
  3. The LED reference designator "D2" is only needed so you'll know where to look on the PCB.

Earlier, I mentioned visualizing "LED" as a four bit wide bit-array. That's my newfound trick of putting a software paradigm onto hardware. Is