In my previous blog, we completed the most basic framework of our configuration; now, we’re picking up where we left off. My objective in this column is simply to use the IDE to do the same thing we did with our command-line batch files in prior blogs. Before introducing too many variables, I need to be confident that I can use the IDE from start to finish, ending up with my FPGA configured and working.
Learning Verilog (or VHDL) will have to come after this. Based on this objective, I’m not going to go through all of the Verilog code. I’m just going to delete everything in the “ledflash_ISE_ver.v” file and copy and paste the code from our old “ledflash.v” file into here.
So, click anywhere in the Verilog code window, and then type Ctrl-A to select all of the text and — yes — delete it! Delete it all! Next, use your favorite text editor to open the “ledflash.v” file we played with in earlier blogs, select all of the text, copy this text, and then paste it into the “ledflash_ISE_ver” window in the ISE. You should now have “endmodule” as line number 56 in the file, as shown below.
We’re well on our way to getting back to exactly where we started, so feel free to take a break and have a soda, coffee, beer, or maybe just a glass of water. But first, use your text editor to open up the other file from our earlier discussions — the “ledflash.ucf” file. Chapter 5 of the tutorial discusses what we’ll be doing next. Again, we’re not going to go through all of the tutorial steps here; just the ones needed to get our simple “ledflash” code into the FPGA.
In my last blog, we created a new “.v” source file — this is the one we just filled with our old
code. Today, we’re going to create the new .UCF (user constraints file). Open the Project
menu in the ISE and select “New Source,” which opens up the “New Source Wizard” as shown
In the wizard, select “Implementation Constraints File,” name it “ledflash_ISE_ver.ucf,” and click
“Next” to finish the process. Again, we’re just trying to get a successful compile / configure
here, so I suggest that you do as I am doing, which is to simply copy and paste the contents of
our old “ledflash.ucf” file into this new “ledflash_ISE_ver.ucf” file as shown below.
We’re really getting close now… so skip ahead to the “Mapping the Design” topic on Page 108 in the Xilinx tutorial. I know that we’re bypassing some details that may be important later, but they really don’t contribute to the cause today.
Click on the label “ledflash (ledflash_ISE_ver.v)” up in the ISE Hierarchy box (in the upper left). Then move down in the Process box (center left) and expand the “Implement Design” label as shown below.
Cross your fingers, hop up and down on one foot for luck, double-click “Implement Design,” and — over the course of the next couple of minutes — observe the green checkmark icons appear next to the “Implement Design,” “Translate,” “Map,” and “Place & Route” items.
Look back in the process window at the “Generate Programming File” item (the third from the bottom in the image above). If you look at the IDE on your screen, you will see that this does not yet have its own green checkmark. Double-click on the “Generate Programming File” item and observe this check mark appear as shown below.
This means that our .BIT configuration file is now complete and is ready to be loaded into the Spartan-6 on our development board. Phew! I don’t know about you, but there seem to be a lot more steps here in the IDE than we had with the command-line operation. However, I suppose that when the configuration spans multiple modules and such, the IDE is the only way to go. Having all of these steps under our belts means that this is a good breaking point. In summary:
- We’ve created the project framework in the IDE (my previous blog)
- We’ve copied our old Verilog code (“ledflash.v”) into the framework
- We’ve copied our old user constraint file (“ledfash.ucf”) UCF into the framework
- We’ve skipped a bunch of tutorial steps that are not relevant to this specific exercise
- We’ve processed our design (translate, map, place-and-route) to the point where we have a .BIT configuration file ready to be loaded into the FPGA
I wish I could tell you that there was just one more step. However, here in the IDE world, there are still several more steps to go, including the use of another piece of software. So I’m afraid that you will have to wait for my next column for me to wrap everything up — at least as far as this tutorial goes. After that, I’m going to start adding some functionality to the design.